1. Field of the Invention
This invention relates to driver circuits which provide a digital input/output interface, and more particularly to driver circuits that can tolerate voltages greater than their power supplies and can produce outputs at voltage levels different from their internal operating voltages.
2. Description of the Related Art
Input and output buffer circuits are commonly used to interface between multiple digital circuits such as memory and DSP (digital signal processing) chips. The buffer driver circuits are often subjected to multiple voltage levels. For example, a driver circuit that is designed to produce a 3.3 volt output, and thus operates from a 3.3 volt output power supply, may receive 5 volt signals if it is connected to a bus that receives 5 volt outputs from other chips. This may result, for example, from the two chips using different types of logic families. Furthermore, the drivers commonly have input and output stages that operate off of separate power supplies, with the input stage isolated from the output power supply to protect it from the output switching noise. The input power supply level may either be the same as or different from the output power supply level, depending upon the application.
Two characteristics that are desirable in a driver circuit of this type are tolerance and compliance. "Tolerance" refers to an ability to withstand voltages greater than the power supply level. For example, a driver that had a 3.3 volt output power supply and could tolerate 5 volts received from a common bus would be said to have a 5 volt tolerance (or whatever greater voltage level it could withstand). "Compliance" refers to the ability to produce a higher voltage on the driver's output than the power supply level used for the main portion of the driver circuitry. A compliance to a higher voltage generally requires that the driver's output power supply be at the higher voltage. For example, a driver with a 3.3 volt input power supply but a 5 volt output power supply capable of producing 5 volt outputs would be said to be compliant to 5 volts.
Higher output than input power supplies are commonly used to bias input protection circuitry, resulting in a tolerance up to the output power supply level (plus about 0.3 volts). However, the user may elect to set the output power supply equal to the input power supply level, perhaps because the only power supply available to the user is at the input power supply level, or because other circuits connected to the common bus could not withstand higher voltages being driven onto the bus. In such a case the driver's tolerance would drop to the input power supply level.
Since it is unpredictable at the manufacturing stage for any given part whether the ultimate user will operate the output power supply at the input power supply level or a higher level, it would be desirable for a driver circuit to be able to maintain both high tolerance and compliance levels regardless of whether the part uses an output power supply equal to or greater than the input power supply level. This challenge is likely to increase in the future as still lower power supply levels are phased in. At present the standard power supply levels are 2.5, 3.3 and 5 volts (all.+-.10%). An effort is now underway to drop the power supply level to 1.8 volts, and thereafter to perhaps 1.0 volts.
Various buffer driver circuits are described in U.S. Pat. Nos. 5,574,389 to Chu, 5,160,855 to Dobberpuhl and 5,387,826 to Shay et al. While exhibiting compliance, the Chu patent is not very tolerant; the Dobberpuhl patent has a good tolerance level but is not compliant; Shay et al. exhibits low levels of both tolerance and compliance.
A simplified illustration of a conventional buffer driver circuit is presented in FIG. 1. It includes an input stage 2 powered from an input power supply terminal 4 with one input 6 which provides a HI or LO input logic signal, and an enable input 8 that receives a signal which either enables or disables the input stage. The input stage produces an output switching signal in the form of a pair of control signals, with one control signal supplied to the gate of a PMOSFET (p-channel metal oxide semiconductor field effect transistor) T1 and a second control signal supplied to the gate of an NMOSFET (n-channel MOSFET) T2. The gates of these transistors act as control inputs for their respective source-drain current circuits. The current circuits of T1 and T2 are connected in series between an output power supply terminal 10 and a ground connection, with the source of T1 connected to terminal 10, the drain of T2 grounded and the drain of T1 connected to the source of T2. The transistors' well connections are indicated by arrows, with the well of T1 connected to its source and the output power supply terminal 10, and the well of T2 connected to its drain and ground. An output terminal 12 is tapped off the connection between the two transistors.
With the input stage 2 enabled and a LO input signal, high voltages are applied to the gates of both T1 and T2, turning T1 OFF and T2 ON. This grounds the output terminal 12 through T2, producing a LO output in response to the LO input on input line 6. With a HI logic input, the input stage 2 sets the gate voltages of both T1 and T2 at ground, turning T1 ON and T2 OFF. This causes the output power supply level to appear at the output terminal 12 via T1. For a TRISTATE input, in which the enable input line 8 is held LO so that the circuit can receive a signal from a common bus connected to the output terminal 12, the input stage 2 applies a HI signal to the gate of T1 and a LO signal to the gate of T2, turning both transistors OFF and allowing the output terminal to float pending the receipt of a signal from the common bus.
With this circuit, if the input power supply is 2.5 volts and the output power supply 3.3 volts, some portion of the input stage must also be powered by 3.3 volts to be able to produce a 3.3 volt gate signal for T1 to turn that transistor OFF during either a LO or a TRISTATE input. But this pierces the input stage's isolation from the output power supply, thus allowing for the possibility of output switching noise getting back into the input stage, and also requires that the wells of the PMOSFETs in the input stage be connected to 3.3 volts.
If, on the other hand, the output power supply is set equal to the input power supply at 2.5 volts rather than 3.3 volts, the circuit can no longer tolerate a 3.3 volt signal applied to the output terminal 12 from some other circuit. This is because the gate voltage applied to T1 to turn it OFF is 2.5 volts, which allows T1 to be turned back ON if the voltage at the output terminal 12 rises above about 3 volts. With a 3.3 volt signal at the output terminal, a substantial current will flow through T1 to the output power supply terminal 10. This current can be on the order of milliamps or greater, as opposed to the usual requirement that leakage currents be limited to not more than about 10 microamps. In essence the output terminal 12 shorts to the output power supply terminal 10 through T1.
The circuit can be made both tolerant and compliant by operating both the input and output power supplies at 2.5 volts, and supplying a third power supply at 3.3 volts for the wells of the PMOS devices in the output stage and also for the gate of T1. However, this requires the addition of a third power supply pin. The addition of any power supplies can result in leakage between the new and the original power supplies, extra ESD (electrostatic discharge) problems, and may require the addition of special circuitry to withstand the higher voltage. It also makes the circuit more difficult to use, since for example the power supplies must be turned ON in the correct sequence. It also makes it more difficult to document and test, since all combinations of power supplies must be tested at all of their limits. The result is more tests, additional cost and in general a more difficult customer support situation.